The present invention relates to a microprogram-controlled type bus control circuit for use in a data processor.
A pipeline control technique is employed to enhance the processing speed of a data processor. One example of such a technique is disclosed in U.S. Pat. No. 4,742,453.
In order to improve the performance of a central processing unit (CPU) of a data processor using a pipeline control technique, attempts are being made to speed up clock cycles used in the data processor.
A microprogram-controlled type CPU for a data processor includes an arithmetic execution unit, an instruction prefetch unit, and a cache memory unit and a system bus interface unit. The system bus interface unit controls a data transfer between the CPU and a main memory or an I/O processor, wherein data transfers among the units are controlled by microinstructions. The operation of a microinstruction in the pipeline control type data processor is disclosed in U.S. Pat. No. 4,644,539.
As a result, a delay time in individual units makes it impossible to let all the units operate in a single clock cycle, and this problem is coped with by dividing each operation into two unit operations. Thus various commands prepared from a microinstruction are given and received among various units in the first clock cycle. Then, the results of command execution are given and received in the next clock cycle. For instance, to take out an instruction or an operand from the cache memory unit, a command from the arithmetic execution unit or the prefetch unit is sent out to the cache memory unit and set in a command register within the cache memory unit in accordance with a microinstruction at the first clock. In the next clock cycle, the cache memory unit executes this command and outputs an instruction or operand data on a bus. In response to what the microinstruction indicates, data is taken in by the units which require the data.
It is now supposed that, when the transfer of a single instruction or operand data unit takes place over two or more clock cycles, the microinstruction is inhibited from execution at the timing of the data being output to the bus and taken in by said units which require the data. As a result, the data will no longer exist on the bus when the execution is resumed. Therefore, if a command is issued in response to a microinstruction immediately preceding the microinstruction inhibited from execution, the data can be transferred, but the CPU performance will deteriorate then. This performance deterioration of the CPU can be prevented by providing a backup circuit for the command register and resuming an execution in response to the content of the initial command register However, if there are a plurality of units taking two or more clocks to transfer data, each unit will require a backup circuit for its command register, inviting an increase in hardware volume.